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Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors

机译:基于双门可控极性晶体管的功率门控差分逻辑样式

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This brief presents a novel power-gating technique for differential cascade voltage switch logic (DCVSL) based on double-gate (DG) controllable-polarity field-effect transistors (FETs). DG controllable-polarity FETs, commonly referred to as ambipolar transistors, are devices whose polarity is online reconfigurable by changing the second gate bias. In this brief, we exploit the online control of ambipolar device polarity to achieve intrinsically power-gated DCVSL circuits bypassing the use of series sleep transistors. We perform circuit-level simulations and comparisons at 22-nm technology node, considering silicon nanowire -based DG controllable-polarity FETs. Experimental results show that ambipolar DCVSL circuits power gated by the proposed technique have on average $6times$ smaller standby power with only $1.1times$ timing penalty with respect to their non-power-gated versions. As compared with unipolar FinFET-based realizations, our proposal is capable to reduce up to $1.9times$ the standby power consumption of a low-standby-power process and, at the same time, increase up to 10% the performance of a high-performance process.
机译:本简介介绍了一种基于双栅极(DG)可控极性场效应晶体管(FET)的差分级联电压开关逻辑(DCVSL)的新型功率门控技术。 DG可控极性FET(通常称为双极性晶体管)是一种极性可通过更改第二栅极偏置在线重新配置的器件。在本简介中,我们利用双极性器件极性的在线控制来实现本质上是功率门控的DCVSL电路,而无需使用串联睡眠晶体管。考虑到基于硅纳米线的DG可控极性FET,我们在22纳米技术节点上进行电路级仿真和比较。实验结果表明,由所提出的技术选通的双极性DCVSL电路的待机功率平均比非功率门控版本小6倍,待机时间仅为1.1倍。与基于单极FinFET的实现相比,我们的建议能够将低待机功耗工艺的待机功耗降低多达1.9倍,同时还可以将高功耗工艺的待机功耗提高10%。表演过程。

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