Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

摘要

Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25$^{ circ}hbox{C}$ to $-40^{circ}hbox{C}$, the sigma/average $(sigma/mu)$ of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that $sigma/mu$ of the gate delay is proportional to $1/T$ for the first time, where $T$ is the absolute temperature.