LOGIC GATE CIRCUIT HAVING LOW SUB-THRESHOLD LEAKAGE CURRENT

摘要

PURPOSE: A logic gate circuit having a low sub-threshold leakage current is provided to reduce the sub-threshold leakage current using only a conventional signal. CONSTITUTION: The logic gate circuit comprises the first and the second voltage generator(50,52) and a CMOS logic gate(54). The first and the second voltage generator are used to drive a PMOS device and an NMOS device of the CMOS logic gate respectively during an active and a standby operation. The first and the second voltage generator and the CMOS logic gate are realized using MOS devices having low threshold voltages. The first and the second voltage generator output voltages(Vpout,Vnout) respectively to drive the PMOS device and the NMOS device of the CMOS logic gate according to an input signal(in). If the voltages satisfy a certain condition, reverse voltage is applied to a gate of an off MOS device during an active and a standby operation, and thus the sub-threshold voltage according to the reduction of the threshold voltage can be reduced.