Semiconductor integrated logic circuit with sequential circuits capable of preventing sub-threshold leakage current

摘要

A semiconductor integrated logic circuit device with a sequential circuit (10, 10A, 10B) includes a transferring section (TM1A, TM1B, TM1 an inverting section (INV1A, INV1B, INV1), a bistable circuit section (INV2A, INV3A, INV2B, INV3B, INV2, INV3, TM2A, TM2B, TM2), and a blocking section (TM3A, TM3B, TM3, TM7) . The transferring section is provided between first and second nodes, and transfers a data signal from the first node to the second node in response to a clock signal. The inverting section is provided between the second node and a third node, and inverts the data signal on the second node to output on the third node as an inverted data signal. The bistable circuit section is connected to the second and third nodes, and holds the data signal. The blocking section is provided between the bistable circuit and the first node, and blocks off sub-threshold leakage current. IMAGE