Methodologies for Evaluating and Measuring Capacitance Mismatch in CMOS Integrated Circuits

摘要

In this brief, two figures of merit and a switched-capacitor filter are used to estimate and measure, respectively, the mismatch between fully integrated capacitors. The theoretical estimations are compared with the experimental results obtained for different layouts fabricated in a test chip using a 0.35- μm CMOS technology.