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首页> 外文期刊>IEEE Transactions on Electron Devices >MONO/POLY technology for fabricating low-capacitance CMOS integrated circuits
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MONO/POLY technology for fabricating low-capacitance CMOS integrated circuits

机译:用于制造低电容CMOS集成电路的MONO / POLY技术

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摘要

A process for the fabrication of CMOS transistors with oxide-isolated source-drain regions that are coplanar with the device channel region is described. The process uses the epitaxial lateral overgrowth technique to selectively grow single-crystal silicon from seed regions that will become the transistor channel regions. The source-drain regions are polycrystalline silicon and are deposited following the selective growth. n- and p-channel device characteristics are presented.
机译:描述了用于制造具有与器件沟道区共面的氧化物隔离的源极-漏极区的CMOS晶体管的工艺。该工艺使用外延横向过生长技术从种子区(将成为晶体管沟道区)选择性地生长单晶硅。源极-漏极区是多晶硅,并在选择性生长之后沉积。介绍了n通道和p通道设备的特性。

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