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Investigation of interface traps at Si/SiO_2 interface of SOI pMOSFETs induced by Fowler-Nordheim tunneling stress using the DCIV method

机译:利用DCIV方法研究Fowler-Nordheim隧穿应力在SOI pMOSFET的Si / SiO_2界面处的界面陷阱

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摘要

The changes of interface trap density and distribution at the Si/SiO~(2)interface in partially depleted SOI MOSFETs were investigated by direct-current current–voltage (DCIV) method before and after Fowler–Nordheim tunnelling stress condition. The equivalent density and energy level of interface trap were obtained by combining the DCIV measurement results with the theoretical calculation using the least square method. It is concluded that the interface trap density increased as applying F–N stress due to the generation of Si dangling bond and the trapped charge at the Si/SiO~(2)interface, and the equivalent energy level of interface trap become close to the midgap with stress time increasing. In addition, interface trap density N ~(IT)as a function of their energy level E ~(IT)can be achieved, which were typical “U-shape” curves, and the interface trap density near midgap increases obviously as the F–N stress time increasing. An effective method is proposed to evaluate the interface state of SOI devices suffered electrical stress or other damages.
机译:在Fowler-Nordheim隧穿应力条件之前和之后,通过直流电流-电压(DCIV)方法研究了部分耗尽的SOI MOSFET中Si / SiO〜(2)界面的界面陷阱密度和分布的变化。通过将DCIV测量结果与使用最小二乘法的理论计算相结合,获得了界面阱的等效密度和能级。结论是,由于Si悬空键的产生和Si / SiO〜(2)界面上的俘获电荷,界面陷阱密度随着施加F–N应力而增加,并且界面陷阱的等效能级接近于间隙时间与压力时间增加有关。另外,可以实现界面陷阱密度N〜(IT)随其能级E〜(IT)的变化,这是典型的“ U形”曲线,并且随着F–的增加,中能隙附近的界面陷阱密度明显增加。 N应力时间增加。提出了一种有效的方法来评估遭受电应力或其他损害的SOI设备的接口状态。

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  • 来源
    《Applied Physics》 |2018年第9期|599.1-599.6|共6页
  • 作者单位

    Institute of Microelectronics, Chinese Academy of Sciences,Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences;

    Institute of Microelectronics, Chinese Academy of Sciences,Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences;

    Institute of Microelectronics, Chinese Academy of Sciences,Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences;

    Institute of Microelectronics, Chinese Academy of Sciences,Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences;

    Institute of Microelectronics, Chinese Academy of Sciences,Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences;

    Institute of Microelectronics, Chinese Academy of Sciences,Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences;

    Institute of Microelectronics, Chinese Academy of Sciences,Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences,University of Chinese Academy of Sciences;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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