Thermal stress induced void formation during 450 mm defect free silicon crystal growth and implications for wafer inspection

摘要

When pulling large diameter Si crystals from a melt close to the Voronkov criterion, small changes in pulling speed and thermal gradient can lead to the formation of voids leading to detrimental pits on the polished wafer surface. The creation of voids is mainly due to the lowering of the vacancy formation energy due to increased thermal compressive stress. The small size and low density of the formed voids when pulling crystals close to the Voronkov criterion conditions are a challenge for wafer surface inspection tools and possible solutions are discussed.