SRAM型FPGA的基于可观性度量的选择性三模冗余方法

摘要

为了增强SRAM型FPGA抗单粒子翻转破坏的能力并减少硬件开销, 提出一种面向查找表的基于可观性度量的选择性三模冗余方法. 首先定义查找表发生单粒子翻转(SEU)故障的一种可观性概念, 并结合概念给出理论计算公式; 然后根据计算出的查找表可观性分布筛选出 SEU 敏感查找表; 最后插入相应的冗余电路. 此方法能够以较小的冗余比例, 使得电路的抗SEU性能接近全三模冗余的效果. 对MCNC'91的18个规模不同的电路进行实验的结果表明, 文中方法平均只需要冗余 37% 的查找表, 并且冗余后电路的抗 SEU 性能为 92.6%, 相比全三模冗余节省了63% 的硬件开销, 说明该方法能够在有效地提高电路的抗SEU性能前提下取得显著的硬件节省效果.%This paper proposed an efficient scheme of observability-oriented selective triple modular redun-dancy (OSTMR) for SEU mitigation in SRAM-based FPGAs. The new technique operated on a lookup-table (LUT) network obtained after the technology mapping stage. A new notion of LUT observability was defined and theoretically calculated using signal probabilities of the nets on a given circuit. Then the entire set of LUTs was evaluated on the basis of signal probability and observability of LUTs. LUTs with higher observability were called SEU-sensitive LUTs and selected. Then the circuit was hardened against SEUs by applying triple modular redundancy to those SEU-sensitive LUTs. The experimental results on MCNC'91 benchmarks show that, with a small loss of reliability, the proposed OSTMR method could greatly reduce the area overhead of the hardened circuit compared with the common triple modular redundancy (TMR). OSTMR triplicates only 37% LUTs on average comparing to full TMR with 200%. Even with such a low area requirement, the circuits pro-duced by the OSTMR technique are observed to achieve a very high SEU immunity by 92.6%.