SILENT ERROR DETECTION IN SRAM-BASED FPGA DEVICES

摘要

Methods and systems for detecting errors in a field programmable gate array are disclosed. One method includes applying a cyclic redundancy check value to a transaction, the transaction including an address and data associated with the address. The method also includes applying a cyclic redundancy check value prior to routing the transaction through a field programmable gate array, and checking the cyclic redundancy check value after routing the transaction through the field programmable gate array to detect errors in the field programmable gate array.