In high-speed SerDes with the half rate structure, the duty of the clock is seriously impor tant, which is the decisive factor for unit intervals. In this article, a 1. 25GHz ring oscillator PLL is es tablished on the 0. 13 μm CMOS process, in which a duty balance circuit is integrated. The result of tes ting shows the stable output clock is 1. 25GHz, and the duty is within the range of 49. 86~51. 21% , and the mean duty is 51. 21%.%半速率高速串行接口同时使用时钟的正/负边沿作为发送数据的定时基准,数据码元的定时长度直接由时钟的占空比决定,因此锁相环的输出时钟的占空比显得尤为重要.本文基于0.13μmCMOS工艺设计实现了一款1.25GHz的高频锁相环.该锁相环基于环形振荡器结构,使用互补相位调节技术实现输出时钟的占空比平衡.流片测试结果表明,该锁相环能够稳定输出1.25GHz的高频时钟,实测输出时钟的占空比能够稳定在49.86％～52.890％的范围内,平均占空比为51.21％.
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