A soft-error-tolerant, 1.25 GHz to 3.125 GHz, 3.18 ps RMS-jitter CPPLL in 40 nm CMOS process

摘要

This paper analyzes the mechanism by which Single-Event-Upsets (SEUs) and Single-Event-transients (SETs) impact on the working condition of the charge-pump-phase-locked-loop (CPPLL) and relevant hardened techniques, and also presents a soft-error-tolerant CPPLL in 40 nm CMOS process. It employs dual-mode interlocking (DMI) and divider-resistance techniques to reduce the soft-error rate caused by natural irradiation. Simulation and laser test results reveal that the DMI and divider resistance techniques could effectively decrease the number of SEU-sensitive nodes in digital parts (frequency divider, phase, and frequency detector) and SET-sensitive nodes in charge pumps. Under 960pJ laser energy, the number of SEU-sensitive nodes in digital parts decreases 96.1%; the number of SET-sensitive nodes in charge pump decline by 83.1%. The proposed soft-error tolerant CPPLL operates under a 1.1 V power supply, consumes 16.6 mW of power, and achieves 1.25 GHz 3.125 GHz working frequency range, 3.18 ps RMS-jitter at a 2.5GHz output frequency.