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Thin-film SOI MOSFET's device physics, characterization and circuit modeling.

机译:薄膜SOI MOSFET的器件物理,表征和电路建模。

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摘要

Silicon-On-Insulator (SOI) technology, which was originally developed for military applications, is finally emerging as a mainstream semiconductor technology. Potential applications such as SRAM, lower power logic and RF IC have been demonstrated by major semiconductor companies. In this thesis, many remaining issues ranging from device physics to circuit modeling have been addressed.; The impacts of silicon film thickness and channel width scaling on Re-oxidized MESA isolation were studied. The subthreshold characteristics and narrow width effect are explained through the geometry of device edge resulted from the sidewall reoxidation.; Several major issues of floating body SOI MOSFET's are addressed in this thesis. The frequency dispersion of output resistance (Rout) in partially depleted device was studied. The effect is explained by the floating body potential fluctuation under the combined influence of hole accumulation in the neutral body and capacitive coupling. Next, capacitive coupling effect was studied theoretically and experimentally. The body charge model for bulk MOSFET was evaluated for its accuracy in predicting the coupling effect. A simple technique was also proposed to characterize the gate coupling factor.; Lastly, a new compact model suitable for circuit simulation of both Partially Depleted and Fully Depleted SOI MOSFET's was developed. A Dynamic Depletion Approach is proposed to model the automatic transition between different depletion modes. Though the joint effort of the graduate researchers in University of California at Berkeley and our group, the model has been installed into Berkeley SPICE 3f4 as BSIM3SOI. Charges and drain current are scaleable with buried oxide and silicon film thickness. Most of the SOI specific effects such as self-heating, parasitic bipolar, non-ideal body contact and backgate effect are included. The C-V model is improved for better accuracy in capacitive coupling prediction. The model is now under evaluation by many companies and SEMATECH.
机译:最初用于军事应用的绝缘体上硅(SOI)技术终于成为主流的半导体技术。大型半导体公司已经证明了SRAM,低功耗逻辑和RF IC等潜在应用。本文解决了从器件物理到电路建模的许多剩余问题。研究了硅膜厚度和沟道宽度缩放对再氧化的MESA隔离的影响。亚阈值特性和窄宽度效应通过侧壁再氧化产生的器件边缘的几何形状来解释。本文解决了浮体SOI MOSFET的几个主要问题。研究了部分耗尽型器件中输出电阻(Rout)的频率色散。这种影响可以通过中性体中空穴积累和电容耦合共同作用下的浮体电势波动来解释。接下来,从理论上和实验上研究了电容耦合效应。评估了体MOSFET的体电荷模型在预测耦合效应中的准确性。还提出了一种简单的技术来表征栅极耦合因子。最后,开发了一种适用于部分耗尽和完全耗尽SOI MOSFET的电路仿真的新型紧凑模型。提出了一种动态耗竭方法来模拟不同耗竭模式之间的自动转换。尽管是由加利福尼亚大学伯克利分校的研究生研究人员和我们的团队共同努力,但该模型已作为BSIM3SOI安装到伯克利SPICE 3f4中。电荷和漏极电流可根据掩埋的氧化物和硅膜的厚度缩放。包括了大多数SOI特有的效应,例如自热,寄生双极,非理想的身体接触和背栅效应。改进了C-V模型以提高电容耦合预测的准确性。现在,许多公司和SEMATECH正在评估该模型。

著录项

  • 作者

    Fung, Ka-hing.;

  • 作者单位

    Hong Kong University of Science and Technology (People's Republic of China).;

  • 授予单位 Hong Kong University of Science and Technology (People's Republic of China).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 1997
  • 页码 155 p.
  • 总页数 155
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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