Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model

摘要

A four-terminal physical subcircuit model for floating body (FB) partially depleted (PD) and near fully depleted (near FD) SOI CMOS devices is presented. The model accounts for the unique characteristics of PD devices associated with the drain (V_(ds)) induced floating body effects. Unlike other models, the proposed circuit model accounts physically for the back MOSFET device, and accurately predicts the bias dependence of the current kink in near FD devices. It allows for proper capacitance scaling and more accurate simulations related to the front and back oxides/channels. Self-heating effects related to the low thermal conductivity of the back oxide are also included. The circuit model is SPICE compatible and provides insights for understanding optimal device design needs for high performance. A simple technique for extracting the model parameters is described. The model is verified by the good agreement of the simulation results with the experimental data. The predictive capabilities of the subcircuit model are supported by circuit level simulation examples.