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Copper CMP Planarity and With-in-Die Rs Improvements on 90nm Cu/Low k Interconnects

机译:90nm Cu / Low k互连的铜CMP平面度和模内Rs的改进

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摘要

One of the benchmarks for Copper CMP performance is planarity. By optimizing copper polish down-force at different stages of the CMP process, with-in-die planarity was improved. Improvements made on planarity were shown to have corresponding gain on with-in-die Rs uniformity and Post-CMP Cu thickness uniformity across different pattern densities. With soft-landing Cu process, defectivity was also improved. For barrier polish, soft-landing had little impact on planarity or electrical properties. In this study, improvements were made over an existing 300mm Cu/low k CMP process at the 90nm node, on planarity, within-in-die Rs uniformity, and defectivity, by optimized copper process conditions.
机译:铜CMP性能的基准之一是平面度。通过在CMP工艺的不同阶段优化铜抛光的下压力,可改善带内芯片的平面度。在平面度上的改进显示出在不同图案密度下,管芯内Rs均匀性和CMP后Cu厚度均匀性都有相应的提高。通过软着陆铜工艺,缺陷率也得到了改善。对于屏障抛光,软着陆对平面度或电性能影响很小。在这项研究中,通过优化铜工艺条件,在90nm节点上对现有的300mm Cu / low k CMP工艺进行了改进,改善了平面度,晶粒内Rs均匀性和缺陷率。

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