PASPAC (Planaraized Al/Silicide/Poly Si with self aligned contact) with low contact resistance and high reliability in CMOS LSIs

摘要

It is widely recognized that a serious restriction on submicron VLSI process is imposed by an interconnection based upon Al-Si system. These prominent problems are, high resistive and non-ohmic contact caused by Si precipitation, leakage of shallow junction due to A1 penetration, low packing density owing to no self aligned contact, poor step coverage and hillock formation, and poor reliability such as stress/electro-migration. Therefore, alternative metallization systems (e.g. CVD-W[1], barrier metal [2], layered structure[3] and A1-Si-Cu[4]) have been proposed to solve these problems. However, these technologies can not totally overcome the concerns, while individual improvement has been accomplished in each technique.