On-state current stress-induced subthreshold I–V instability in SiC DMOSFETs

摘要

The reliability of SiC DMOSFETs has been studied in the past several years, including gate oxide reliability with time-dependent dielectric breakdown measurements [1–2], and threshold voltage stability with gate-bias and On-state current stress measurements [2–4]. For example, it has been reported that gate-bias stressing causes a time-dependent shift in threshold voltage, and that an On-state current stress causes a slightly larger threshold-voltage instability [4]. Furthermore, it has been observed that an increase in Off-state leakage current can occur at high temperatures but which can be reduced with the application of a negative gate-bias, indicating an increase in subthreshold-voltage leakage current [5]. It has also been reported that the bias-stress induced threshold-voltage instability increases at increasing temperatures for some SiC MOSFET sample sets [6].