The variation of threshold voltages associated with various applied gate voltages at different temperatures on FinFET devices

摘要

NFinFET devices with channel length 100nm and 120nm fabricated on SOI (silicon on insulator) wafers are measured to show I-V and I-V characteristic curves. I-V characteristic curves demonstrate suppressed I's associated with Drain Induced Barrier Lowering (DIBL) and Punch-through effects. I-V characteristic curves are then roughly fitted by using the traditional current-voltage formula to obtain V at different temperatures. The measured curves along with fitted curves are presented simultaneously in each case for comparison, where an algorithm is deliberately introduced to fix V at V=0.25V and make k and λ in common in either case. Several conclusions are then made to understand the phonon effects on the threshold voltages and thus electrical performances. For one case, the higher temperatures enhance the electric performances by lowering the threshold voltages at V=0 volt. On the other hand, the higher temperatures degrade the electrical performances by raising the threshold voltages at V=0.5 volt or higher. And possibly a model is proposed to understand the underlying physical properties.