Review of Advanced Copper Interconnection Process -Deposition of low resistance and low stress Cu interconnection layer -

摘要

Reduction of the resistance and resistivity is an important task in the manufacture of high speed MOS LSI's. However, such low resistivity layer cannot obtain practically in the Cu interconnection, specifically in the 0.13 and 0.10 μm wide layer. This is due to that narower net cross-sectional area is manufactured when the layer coated by thick barrier layer, such as by Ta and TaN. Resistivity of highly stressed Cu layer is much higher than that of bulk Cu layer. This paper describes the deposition and formation of low resistance and low resistivity resistivity Cu layer.