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Piezoresistive membrane deflection test structure for the evaluation of hermeticity in low cavity volume MEMS and microelectronic packages

机译:用于评估低腔体积MEMS和微电子封装中的气密性的压阻膜挠曲测试结构

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This paper details the design, fabrication and characterisation of a piezoresistive membrane deflection test structure for the electrical evaluation of hermeticity in low cavity volume package. This test structure uses the 0-level silicon cap, defined in the MultiMEMS foundry service, as a deflecting membrane to electrically monitor changes in package cavity pressure over time. The hermeticity of the package can then be determined in real-time and low leak rates can be measured using a pressurisation stage, which also accelerates the test. The minimum detectable leak rate of the test structure without test acceleration is 6.9×10-12 atm.cm3.s-1, which is two orders of magnitude lower than the limit of the traditional helium fine leak test method.
机译:本文详细介绍了用于低腔体积封装的气密性电气评估的压阻膜挠曲测试结构的设计,制造和表征。该测试结构使用MultiMEMS代工服务中定义的0级硅盖作为偏转膜,以电监控封装腔内压力随时间的变化。然后可以实时确定包装的气密性,并且可以使用加压阶段来测量低泄漏率,这也可以加快测试速度。在没有测试加速度的情况下,测试结构的最小可检测泄漏率为6.9×10-12 atm.cm3.s-1,比传统的氦气精细泄漏测试方法的极限低两个数量级。

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