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Electrical Test Structure for the Measurement of Hermeticity in Electronic and MEMS Packages With Small Cavity Volumes

机译:用于测量小空腔体积的电子和MEMS封装中气密性的电气测试结构

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The design, fabrication, and characterization of a piezoresistive membrane deflection test structure for the electrical evaluation of hermeticity in low cavity volume packages is discussed. This test structure uses the zero-level silicon cap as a deflecting membrane to electrically monitor changes in package cavity pressure over time. The hermeticity of the package can then be determined in real-time and low leak rates can be measured using a pressurization stage, which also accelerates the test. The minimum detectable leak rate of the test structure without acceleration has been measured at $6.9times,10^{-12}~{rm atm}cdot{rm cm}^{3}cdot{rm s}^{-1}$, which is two orders of magnitude lower than the limit of a traditional helium fine leak test.
机译:讨论了用于小腔容积包装中气密性电气评估的压阻膜挠曲测试结构的设计,制造和表征。该测试结构使用零级硅盖作为偏转膜来电监控封装腔内压力随时间的变化。然后可以实时确定包装的气密性,并且可以使用加压阶段来测量低泄漏率,这也可以加快测试速度。在没有加速度的情况下测试结构的最小可检测泄漏率已在 $ 6.9倍,10 ^ {-12}〜{rm atm} cdot {rm cm}下进行了测量^ {3} cdot {rm s} ^ {-1} $ ,比传统的氦气细漏试验的极限低两个数量级。

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