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Piezoresistive membrane deflection test structure for the evaluation of hermeticity in low cavity volume MEMS and microelectronic packages

机译:低腔体积MEMS和微电子封装评估气密性的压阻膜偏转试验结构

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This paper details the design, fabrication and characterisation of a piezoresistive membrane deflection test structure for the electrical evaluation of hermeticity in low cavity volume package. This test structure uses the 0-level silicon cap, defined in the MultiMEMS foundry service, as a deflecting membrane to electrically monitor changes in package cavity pressure over time. The hermeticity of the package can then be determined in real-time and low leak rates can be measured using a pressurisation stage, which also accelerates the test. The minimum detectable leak rate of the test structure without test acceleration is 6.9×10-12 atm.cm3.s-1, which is two orders of magnitude lower than the limit of the traditional helium fine leak test method.
机译:本文详细说明了低腔体容积封装中对气密性电气评估的压阻膜偏转试验结构的设计,制造和表征。 该测试结构使用在多端式铸造服务中定义的0级硅帽,作为偏转膜,以电信监测封装腔压力的变化随时间。 然后可以使用加压阶段测量实时的包装的气密性,并且可以使用加压阶段测量低泄漏速率,这也加速了测试。 测试结构的最小可检测泄漏率没有测试加速度为6.9× 10-12atm.cm3.s-1,这两个数量级低于传统氦精细泄漏测试方法的极限。

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