Low power and high performance SOI SRAM are the main key issues and has become vital component in modern VLSI systems. For portal gadgets and related applications, low power SOI SRAM array design is essentially important to sustain the extended battery life. Normally, large power is being consumed during charging/discharging by bit lines. To reduce the power consumption and access time for write/read operations, the new technique is introduced in the Reliable Fast (RF) SOI SRAM design. The proposed new techniques employed in the SOI SRAM cell have proved to minimize the write power consumption about 80% and read power consumption about 49% compared to the conventional cell. The read delay and stability of the proposed cell are also improved in the new design SRAM cell.
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