DEVELOPMENT OF A 3D WAFER-LEVEL RE-ROUTING USING DIELECTRIC LAMINATION TECHNOLOGY

摘要

Technical developments in wafer level packaging of electrical devices are to be in line with the more general packaging trends like volume and footprint reduction. The realization of highly miniaturized System in Package (SiP) or thin stackable packages containing active and passive devices, the formation of 3-D interconnection patterns, making interconnection through the silicon wafer, connecting top to bottom, requires new or improved manufacturing technologies. This paper will present the approaches for the technological realization of 5x5mm2 “eGrain” prototypes based on Berkeley structures. These “eGrain” structures combine different functional layers, to be realized in the smallest size, to achieve the intended overall dimension. Therefore the use of the surface of the silicon wafer as a substrate for the volume components (R, L, C) is needed.