VLSI-CMOS Device Technology Scaling Landscape Based on Fully-Depleted SOI and 3D-Finfet Technologies for the Internet of Everything Era

摘要

System- and process-level innovations based on VLSI-CMOS technologies are the drivers to continue Moore's Law. Especially in the last decade an ever-increasing component integration on SoC's has driven cost scaling and will continue to do so while approaching the IoT and wearable device area [1]. To keep pace with the manufacturing cost per device scaling an acceleration of new processing methods, concepts and materials has been introduced, such as local strained Si, high-k metal gate, ultra-low-k, 3D FinFET and FDSOI devices [2-5]. New integration techniques like double and quadruple patterning are needed since EUV lithography cannot be easy introduced in high-volume manufacturing. The inflection on the cost per gate trend can be intercepted by differentiated technologies that serve markets for the respective applications such as 22-nm and 12-nm FDSOI. Those technologies offer a wide variety and individualism for designs to serve the IoT/E era perfectly. SoC innovations need to focus on 3D multi-die package integrations on system level.