As the development of microelectronics is still driving towards further miniaturization, Flip Chip and Waferlevel CSP technology have been widely accepted as a means for maximum miniaturization with additional advantages. Both package types do generally not include an encapsulation layer, but only die passivation and dielectric rewiring layers respectively. To fulfill the reliability demands of harsh environment applications, the use of an additional encapsulant is crucial. This is especially true for future applications as high temperature packages or miniaturized SiPs (system in package), where the encapsulant is protecting the sensitive structures generated on wafer level. After package assembly on the substrate, typically underfill materials are used to realize the liquid post encapsulation providing maximum protection and thus increased reliability. As these underfilling processes mean an extra process step, technologies are developed to replace post-assembly underfilling. A cost-effective way is to apply an encapsulant layer directly on bumped wafers and thus generate additional protection. Processes for wafer level encapsulation include wafer level molding, wafer level liquid encapsulation and wafer level printing, all three technologies bearing individual advantages and disadvantages. For wafer level SiP encapsulation the encapsulant acts not only as a simple mechanical protection of the active layer, the encapsulation can provide additional functionality. A 3D structuring of the encapsulation layer allows the integration of e.g. optical devices as micro lenses, assembly structures as grooves or adjustment aids. Using metallization and structuring techniques on the encapsulation layer in combination with an interlayer connection to the active structures on the wafer e. g. by solder bumps a wafer level rerouting process can be realized for a redistribution of contact pads with a relaxed pitch. Shielding structures and RF functionality by integrated antennas could be established in this way as well. Within this paper encapsulation technologies as transfer molding and printing have been investigated, focusing on the feasibility of reliable wafer encapsulation and the suitability of current materials. For these processes the potential of 3D structuring during the encapsulation has been evaluated. An electroless metallization process and laser techniques for structuring the metallization layer have been investigated for reliable interconnections. Summarized this paper presents the process development and feasibility of wafer level encapsulation technologies for SiP solutions.
展开▼
