Thin gated Dielectric TFTs using damascene-gate structures

摘要

As flat panel display sizes and resolutions increase, it becomes necessary to improve the electronic performance of the TFT array. This requires the use of low-resistance gate lines and faster switching TFTs, which can be acieved by using thick gate metal and thin gate dielectrics, respectively, However, in covementiolnal inverted-staggered devices, thick gates crate a harge stpe which then requires a thick gate dielectric for adequate coverage. The approach presented here embeds the gate in a passivation layer so that thin gate dielectrics can be deposited on a relativley flat surface. More importantly, this structre is achieved withou increasing the number of masks used in conventional processes and does not require nay chemical-mechanical plishing of the surface. Profilometry reveals a smooth surface with step mismatch as low as 10 nm. Gate dielectrics as thin as 50 nm were deposited and excellent TFT performance is obtained.