Impact of 0.10 μm SOI CMOS with body-tied hybrid trenchisolation structure to break through the scaling crisis of silicontechnology

摘要

A hybrid-trench-isolation (HTI) technology is proposed to overcomethe scaling limitations caused by the difficulty of gate thinning andincreased soft error rate at the 0.1 μm era. It is revealed that asignificant speed improvement against bulk is achieved by using thebody-tied structure without floating-body-relate speed deterioration. Atwo-order reduction in the soft error rate for an HTI-SOI 4M-bit SRAMwas demonstrated as compared with bulk structure. Moreover, it is shownthat full trench isolation in the HTI offers excellent isolationcharacteristics to realize the one-chip integration of analog anddigital LSI's. It is concluded that SOI technology with HTI structure isone of the solutions against the scaling limitations