Impact of 0.18μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

摘要

A 0.18μm SOI CMOS technology using hybrid trench isolation with high resistivity substrate has been proposed for RF/analog applications and its feasibility is verified. The hybrid trench isolation is a successful combination of the partial trench isolation that has thin SOI layer under the isolation oxide and the full trench isolation that has no SOI layer. Evaluating the SOI MOSFET fabricated by using this technology, advantages of SOI MOSFETs are clarified, based on the idea of electrostatic induction between the devices and substrate. High body-fixing ability of this technology and high-quality on-chip inductance are demonstrated.