CMOS and interconnect reliability ESD, soft errors and backend reliability issues for nanoscale CMOS technologies

机译：纳米级CMOS技术的CMOS和互连可靠性ESD，软错误和后端可靠性问题

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《Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International》||p.931-931|共1页
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Banerjee K.; Blish R.;
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1. An Efficient Design of Sequential Digital Circuits to Reduce Soft Errors in Nanoscale CMOS Technology [J] . K. Aditya, M. Sivakumar, B. K. V. Prasad, International Journal of Engineering Studies . 2012,第1期

机译：一种有效的顺序数字电路设计，可减少纳米级CMOS技术中的软错误
2. A 0.11 μm CMOS technology featuring copper and very low κ interconnects with high performance and reliability [J] . Yoshihiro Takao, Hiroshi Kudo, Junichi Mitani Microelectronics & Reliability . 2002,第1期

机译：采用铜和极低κ互连的0.11μmCMOS技术，具有高性能和可靠性
3. Reliability Analysis of P+ Pickup on Anti-ESD Performance in Four CMOS Low-Voltage Technology Nodes [J] . Chen Shen-Li, Lee Min-Hua IETE Journal of Research . 2016,第6期

机译：P +拾取器在四个CMOS低压技术节点中抗ESD性能的可靠性分析
4. CMOS and interconnect reliability interconnect, plasma damage, and ESD reliability [C] . Seung Kang, Nogami, T. Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International . 2005

机译：CMOS和互连可靠性互连，等离子损坏和ESD可靠性
5. Reliability and performance issues in nanoscale SOI CMOS. [D] . Ioannou, Dimitri P. 2007

机译：纳米SOI CMOS中的可靠性和性能问题。
6. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology [O] . Jose Luis Muñoz-Gamarra, Arantxa Uranga, Nuria Barniol 2016

机译：使用65 nm CMOS技术单片集成的CMOS-NEMS铜开关
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CMOS and interconnect reliability ESD, soft errors and backend reliability issues for nanoscale CMOS technologies

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