An Efficient Design of Sequential Digital Circuits to Reduce Soft Errors in Nanoscale CMOS Technology

摘要

We initiate some soft-error-tolerant Sequential elements which evaluate the benefits and drawbacks of several state-of-the-art designs, and determines optimal designs for advanced technology. The designs induce non-trivial area, power overhead. In modern technologies, logic elements are becoming increasingly vulnerable to soft errors. Several designs today implement extensive error detection and correction. In this design we use smaller and faster transistors. In this work, we will analyze the impact of soft errors on latches and flip-flops in nanoscale CMOS technology. Here each design is compared with a standard, non-SER tolerant latch or flip-flop, and then assess each design based on SER protection, area, and power overhead.