A 0.11 μm CMOS technology featuring copper and very low κ interconnects with high performance and reliability

摘要

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low κ(<2.7) interocnnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm~2 six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. eight-level interconnects are fabricated with seven level of Cu/ VLK interconnect and one level of Al/SiO_2 interconnect.