首页> 外文会议>SMTA international conference >ASSEMBLY AND DESIGN CHALLENGES FOR NEW GENERATION 0.4/0.4MM PITCH PACKAGE ON PACKAGE (POP) AND 0.3MM PITCH CHIP SCALE PACKAGE (CSP)
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ASSEMBLY AND DESIGN CHALLENGES FOR NEW GENERATION 0.4/0.4MM PITCH PACKAGE ON PACKAGE (POP) AND 0.3MM PITCH CHIP SCALE PACKAGE (CSP)

机译:新一代0.4 / 0.4毫米间距封装(POP)和0.3毫米间距芯片尺寸封装(CSP)的组装和设计挑战

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摘要

Miniaturization and the integration of a growing number of functions in portable electronic devices require an extremely high packaging density for the electronic components. One way to increase the packaging density is to reduce the size of the packages stack them with as Package on Package (PoP) and at the same time increase the density of the I/Os. This means that the size and pitch of solder balls or pads in the electronic component packages will continue to shrink and that component stacking with so called Package on Package (PoP) will be heavily used. Another important factor is that not only is the area density increasing and the drive to make portable electronics thinner also drivers thinner components and thereby warpage becomes one of the key challenges. The use of fine pitch CSP and PoP component's, equal and below 0.4mm pitch, poses a number of challenges for PCB Design, SMT Assembly process and Reliability. First, a feasible assembly process must be achieved. The assembly process ranges all the way from screen-printing, dipping in flux or paste, reflow soldering in air or nitrogen and in many cases underfill of CSP's and PoP's. Many factors influence the quality of the assembly process and with the reduced pitch the process capabilities for both assembly and PCB fabrication will be tested to its limit and beyond. The basic processes to control are screen-printing, pick & place, reflow soldering with or without the aid of Nitrogen and underfill. Second, the right materials (such as PCB material, PCB surface finish, solder paste, dipping flux or paste and underfill) and PCB design need to be selected to ensure a high yielding, cost effective and reliable interconnect. Of course the mechanics of the products makes a big difference as well but it is very product dependant and many of today's products leave little room for designing the mechanics in the most reliable way due to total cost and overall looks of the product. This paper will discuss different design & layout alternatives and assembly & material selection alternatives for 0.3-0.4mm pitch CSP's and 0.4/0.4mm pitch PoP devices and the challenges with those. Different stencil types and dipping materials together with air vs. nitrogen refiow is a big part of this study.
机译:便携式电子设备的小型化和越来越多的功能的集成要求电子部件具有极高的封装密度。增加包装密度的一种方法是减小与“堆叠式包装”(PoP)一起堆叠的包装的尺寸,同时增加I / O的密度。这意味着电子组件封装中的焊球或焊盘的尺寸和间距将继续缩小,并且将大量使用与所谓的封装上封装(PoP)堆叠的组件。另一个重要因素是,不仅面积密度增加,并且使便携式电子产品更薄的驱动力也使组件更薄,因此翘曲成为关键挑战之一。等于和小于0.4mm间距的细间距CSP和PoP组件的使用给PCB设计,SMT组装工艺和可靠性提出了许多挑战。首先,必须实现可行的组装过程。组装过程包括丝网印刷,浸入助焊剂或焊膏,在空气或氮气中进行回流焊接以及在许多情况下CSP和PoP的底部填充。许多因素都会影响组装过程的质量,并且随着间距的减小,组装和PCB制造的过程能力都将受到极限测试。控制的基本过程是丝网印刷,拾取和放置,在有或没有氮气和底部填充的情况下进行回流焊接。其次,需要选择正确的材料(例如PCB材料,PCB表面处理,焊膏,浸渍助焊剂或焊膏和底部填充胶)和PCB设计,以确保高产量,经济高效且可靠的互连。当然,产品的机械原理也有很大的不同,但是它与产品密切相关,并且由于产品的总成本和整体外观,当今的许多产品几乎没有以最可靠的方式设计机械结构的空间。本文将讨论0.3-0.4mm间距CSP和0.4 / 0.4mm间距PoP器件的不同设计和布局替代方案以及组装和材料选择替代方案以及这些挑战。不同的模板类型和浸入材料以及空气与氮气回流是这项研究的重要内容。

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