Static Noise Margin of the Full DG-CMOS SRAM Cell Using Bulk FinFETs (Omega MOSFETs)

摘要

The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 μm{sup}2 was achieved by 90 run node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V{sub}(CC) of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.