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SRAM cell with independent static noise margin, trip voltage, and read current optimization
SRAM cell with independent static noise margin, trip voltage, and read current optimization
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机译:具有独立静态噪声容限,跳闸电压和读取电流优化功能的SRAM单元
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摘要
An SRAM memory cell structure utilizing a read driver transistor and a column select write transistor, and a method of operating the same. The SRAM memory cell comprises first and second cross-coupled inverters, having a first and second latch nodes, respectively. The cell further comprises a first write pass transistor connected between the first latch node of the first inverter and a first pass node, and a first wordline pass transistor connected between the first pass node and a first bitline. The cell also includes a first read driver connected between the first pass node and a source potential, and a control terminal of the first read driver connected to the second latch node of the second inverter.
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