Implementation of Cu metallization for high-speed, fine geometry IC devices is progressing rapidly throughout the industry. Due to the metallurgical constraints associated with this material, it is necessary to provide for barrier and top metal layers suited to the interconnect technology of choice (i.e., flip chip or wire bond). In the case of products intended for wire bonding, the Cu is generally coated first with a diffusion barrier layer such as TaN, which is then topped off with Al or an Al-rich alloy to form the final interconnect level. In addition to the well-characterized effect of various alloying elements such as Si and Cu upon the chemical and mechanical stability of the Al metal layer, the presence of the underlying Cu and barrier metal layers has been found to influence the formation of defects on the bond pad surface. Specifically, residual stresses associated with metal layer deposition and CMP processes have been found to influence the formation of hillock and pit hole defects in the final metal layer. This paper explores the mechanisms of formation for these kinds of surface defects in a bond pad stack consisting of approximately 12k angstroms of Al-0.5%Cu atop approximately 9k angstroms of Cu, separated by a thin layer of Ta. The impact of these defects on the assembly interconnection process, and their tendency to provide nucleation sites for moisture-induced corrosion, are characterized. Wafer fabrication processes having a direct impact on defect formation are reviewed, along with potential defect-reduction methods
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