Defect Analysis of Semiconductor Memory Device Arrangement of edge pads and package bonding center pads

摘要

1. The technical field to which the invention described in the claims belongs;Semiconductor memory device having an adhesion center pad and a failure analysis edge pad;2. Technical challenges to be solved by the invention;The present invention provides a pad arrangement structure in which the defect analysis edge pad of the prior art is disposed in the scribe line area outside the chip and the package lead wire bonding center pad is disposed in the center of the chip to reduce the chip size and each pad can be used independently .;3. The point of the solution of the invention;The present invention relates to a semiconductor memory device comprising at least two or more memory cell array block-containing chips, wherein the semiconductor memory device is arranged at the center between the memory cell array blocks to transfer data inside the chip to the outside of the chip, And a plurality of failure analysis edge pads arranged at an edge of the chip to test an operation state of the chip, and a plurality of failure analysis edge pads arranged between the chips, Includes a scribe line area that arranges the pads side by side.;4. Important Uses of the Invention;And is suitably used in a semiconductor memory device having a pad.