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Cu Pillar flip chip assembly: Chip attach process failure mode study

机译:Cu Pillar倒装芯片组装:芯片附着过程故障模式研究

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An experiment is conducted to study failure mechanism during flip chip attach process for Cu Pillar bumped Si device that uses mass reflow assembly technology. A three-leg design of experiment (DOE) is conducted, which includes two UBM sizes, two different Cu pillar height, and with / without polyimide option to collect basic failure information. Finite element software is used to correlate the failure mode and identify the Si — Cu pillar bump — substrate interactions. Based on the experiment and finite element analysis results, a simple shallow beam mechanical model was recommended to be a basic start point of Cu Pillar flip chip assembly technology application. Results are discussed in details.
机译:进行了一项实验,以研究采用大规模回流装配技术的Cu Pillar凸点Si器件的倒装芯片附着过程中的失效机理。进行了三腿实验设计(DOE),其中包括两个UBM尺寸,两个不同的Cu柱高,以及带有/不带有聚酰亚胺选项的基本故障信息收集方法。有限元软件用于关联故障模式并识别Si-Cu柱状凸点-基板之间的相互作用。根据实验结果和有限元分析结果,建议采用简单的浅梁力学模型作为Cu Pillar倒装芯片装配技术应用的基本出发点。结果进行了详细讨论。

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