assembling; copper; lead bonding; low-k dielectric thin films; reliability; tape automated bonding; C4 reflow; CPI effect; Cu; GLOBALFOUNDRIES technology node; TCB-NCP processes; advanced node silicon devices; capillary underfill process; chip-package-interaction effect; cold joints; electrical performance; low k stress; low-k chip; package BOM selection; pillar bump; pitch joints; reliability studies; size 28 nm; thermocompression bonding assembly process; thermomechanical stress; ultra low-k dielectrics; Assembly; Bonding; Flip-chip devices; Joints; Reliability; Stress; Substrates;
机译:低温热压结合的Cu / Sn-Ag柱状凸点的结合性能和可靠性
机译:铜柱凸块倒装芯片直接Cu-Cu键合方法的比较研究
机译:PCB焊盘金属表面处理对板载芯片(COB)组件的Cu-Pillar / Sn-Ag微凸点焊接可靠性的影响
机译:Cu / Low-K芯片Cu柱凸块Cu柱凸块的热压缩组装工艺及可靠性研究
机译:BEoL Cu / Low-k叠层的3-D断裂研究,以评估和减轻回流过程中的CPI风险。
机译:晶圆级Cu-Cu热压键合的表面预处理方法研究
机译:用焊接铜柱凸块的外围倒装芯片互连的微结构观察和可靠性行为