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Thermo-compression bonding for 2.5D fine pitch copper pillar bump interconnections on TSV interposer

机译:TSV中介层上2.5D细间距铜柱凸点互连的热压键合

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The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There is active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, there is increased in the demand for fine pitch copper pillar bumping due to the lower silicon node, chip size reduction and TSV technology. Fine pitch interconnections are required in 2.5D and 3DIC integration for the demands of electrical continuity and high performance. In the existing interconnection methods, solder micro bumps have received a great deal of attentions because of its low material and process cost [2]. The major difference of copper pillar FC bonding process comparing to traditional FC bonding process is the reduction of the solder volume on each solder bump. As a result, there is no advantage of self-alignment of the solder during solder reflow process. Flip-chip bonder having accurate chip placement capability is needed to ensure good solder joint formation. Conventional reflow method is still applicable for sizable solder bump of diameter being greater than 100 μm and larger than 150μm pitch [3]. The post underfill processes such as capillary underfill (CUF) and molded underfill (MUF) can be followed after the solder joints are formed. On the other hand, when the pitch of bumps and/or the thickness of the FC go down further, FC with copper pillar bumps bonded by TC process would be one of the solutions for fine-pitch FC applications. It has been shown that the bump pitch can be reduced to as small as 50 μm (inline pitch). This process also allows for better control on the solder squeezed out effec- . However this process requires tight control on (i) the planarization between the FC and the bonding substrate and (ii) the stand-off of each solder joint. Good process parameters have to be established to ensure no solder collapse or open joint.
机译:诸如智能电话和平板电脑之类的便携式电子设备的使用导致对更多功能,更小尺寸和更低功耗要求的高需求。为了应对这些挑战,电子封装设计使用了具有细间距凸起的较薄芯片。带有硅通孔(TSV)的2.5D和3D IC封装正在积极开发中。在2.5D和3D IC系统中,除了增加的电路密度以外,更紧密的互连还提供了更高的性能和更低的功耗[1]。另外,由于较低的硅节点,减小的芯片尺寸和TSV技术,对细间距铜柱凸块的需求也增加了。 2.5D和3DIC集成中需要细间距互连,以实现电气连续性和高性能。在现有的互连方法中,焊料微凸块由于其材料和工艺成本低而受到了广泛的关注[2]。与传统的FC键合工艺相比,铜柱FC键合工艺的主要区别在于减少了每个焊料凸点上的焊料量。结果,在焊料回流过程中没有焊料自对准的优点。需要具有精确的芯片放置能力的倒装芯片键合机以确保良好的焊点形成。传统的回流方法仍然适用于直径大于100μm且大于150μm间距的较大焊料凸块[3]。形成焊点后,可以执行诸如毛细管底部填充(CUF)和模制底部填充(MUF)之类的后底部填充工艺。另一方面,当凸块的间距和/或FC的厚度进一步减小时,具有通过TC工艺结合的铜柱凸块的FC将是用于小间距FC应用的解决方案之一。已经表明,可以将凸块间距减小到小至50μm(在线间距)。此过程还可以更好地控制挤出的焊料。但是,此过程需要严格控制(i)FC和粘合基板之间的平面化,以及(ii)每个焊点的支座。必须建立良好的工艺参数,以确保没有焊料塌落或开路。

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