An experimental verified model for Cu electrodeposition simulation for the filling of high aspect ratio through silicon vias

摘要

The super-filling of high aspect ratio through silicon vias (TSVs) is a technical challenge for 3D integration. For optimizing the super-filling, the numerical simulation models of copper electro-deposition with suppressor and accelerator are founded. The arbitrary Lagrange-Eulerian (ALE) method for solving moving boundaries in finite element model (FEM) is used to simulate the electrochemical process. The simulation can predict the behavior of Cu electro-deposition, and the influence of concentration of suppressor was investigated. The simulations of the bottom-up copper electro-deposition are verified by experiment results. TSVs with diameter of 20 μm and depth of 200 μm without voids or seams have been achieved in the experiments.