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Plasma Doping on 68nm CMOS Device Source/Drain Formations

机译:68nm CMOS器件源/排水形成等离子体掺杂

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The plasma doping technique offers unique advantages over conventional beam line systems, including system simplification, lower cost, higher throughput, and device performance equivalence or improvement. Plasma doping has been first used on 68nm CMOS device source and drain formations. A PMOS device was doped by B{sub}2H{sub}6 plasma doping and an NMOS device was doped by AsH{sub}3 plasma doping. The devices fabricated by plasma doping processes were intensively evaluated in this paper. In addition to higher throughput, CMOS devices, both PMOS and NMOS devices, fabricated by plasma doping processes showed improved electrical performance to those fabricated by conventional beam line ion implantation, including ~10-20 percent lower contact resistances, similar threshold and sub-threshold characteristics, ~10 percent higher drive currents and transconductances, and better device performance curves.
机译:等离子掺杂技术提供了传统的光束线系统的独特优势,包括系统简化,降低成本,更高的吞吐量和设备性能等效或改进。已经在68nm CMOS器件源和排水形成上使用等离子体掺杂。由B {Sub} 2H {Sub} 6等离子体掺杂掺杂PMOS装置,并且通过灰分{Sub} 3等离子体掺杂掺杂NMOS器件。本文集中评价等等离子体掺杂工艺制造的装置。除了较高的产量,由等离子体掺杂工艺制造的PMOS器件,PMOS和NMOS器件,对由常规光束线离子植入制造的那些,包括〜10-20%的接触电阻,类似的阈值和子阈值(包括〜10-20%)特点,〜10%的驱动电流和跨导,更好的设备性能曲线。

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