首页> 外国专利> COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES EMPLOYING PLASMA-DOPED SOURCE/DRAIN STRUCTURES AND RELATED METHODS

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES EMPLOYING PLASMA-DOPED SOURCE/DRAIN STRUCTURES AND RELATED METHODS

机译:使用等离子体掺杂源/漏结构的互补金属氧化物半导体(CMOS)设备及相关方法

摘要

Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods are disclosed. In certain aspects, a source and drain of a CMOS device are formed at end portions of a channel structure by plasma doping end portions of the channel structure above solid state solubility of the channel structure, and annealing the end portions for liquid phase epitaxy and activation (e.g., superactivation). In this manner, the source and drain can be integrally formed in the end portions of the channel structure to provide coextensive surface area contact between the source and drain and the channel structure for lower channel contact resistance. This is opposed to forming the source/drain using epitaxial growth that provides an overgrowth beyond the end portion surface area of the channel structure to reduce channel contact resistance, which may short adjacent channels structures.
机译:公开了采用等离子体掺杂的源极/漏极结构的互补金属氧化物半导体(CMOS)器件以及相关方法。在某些方面,通过在沟道结构的固态溶解度之上对沟道结构的等离子体掺杂的端部进行掺杂,并在该端部进行退火以进行液相外延和活化,从而在沟道结构的端部处形成CMOS器件的源极和漏极。 (例如,超激活)。以这种方式,源极和漏极可以整体地形成在沟道结构的端部中,以在源极和漏极与沟道结构之间提供共延的表面积接触,以降低沟道接触电阻。这与使用外延生长形成源极/漏极相反,该外延生长提供超过沟道结构的端部表面积的过度生长以减小沟道接触电阻,这可能使相邻的沟道结构短路。

著录项

  • 公开/公告号US2017352662A1

    专利类型

  • 公开/公告日2017-12-07

    原文格式PDF

  • 申请/专利权人 QUALCOMM INCORPORATED;

    申请/专利号US201715602326

  • 发明设计人 JEFFREY JUNHAO XU;

    申请日2017-05-23

  • 分类号H01L27/092;H01L21/8234;H01L29/66;H01L29/417;H01L29/78;

  • 国家 US

  • 入库时间 2022-08-21 12:58:01

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