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Plasma Doping on 68nm CMOS Device Source/Drain Formations

机译:在68nm CMOS器件源极/漏极结构上进行等离子体掺杂

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摘要

The plasma doping technique offers unique advantages over conventional beam line systems, including system simplification, lower cost, higher throughput, and device performance equivalence or improvement. Plasma doping has been first used on 68nm CMOS device source and drain formations. A PMOS device was doped by B2H6 plasma doping and an NMOS device was doped by AsH3 plasma doping. The devices fabricated by plasma doping processes were intensively evaluated in this paper. In addition to higher throughput, CMOS devices, both PMOS and NMOS devices, fabricated by plasma doping processes showed improved electrical performance to those fabricated by conventional beam line ion implantation, including ~10-20 percent lower contact resistances, similar threshold and sub-threshold characteristics, ~10 percent higher drive currents and transconductances, and better device performance curves.
机译:等离子体掺杂技术提供了优于常规束线系统的独特优势,包括系统简化,成本更低,通量更高以及等效或改进的设备性能。等离子体掺杂首先用于68nm CMOS器件的源极和漏极结构。通过B2H6等离子体掺杂来掺杂PMOS器件,通过AsH3等离子体掺杂来掺杂NMOS器件。本文对通过等离子体掺杂工艺制造的器件进行了深入评估。除了更高的产量外,通过等离子体掺杂工艺制造的CMOS器件(PMOS和NMOS器件)与传统束线离子注入制造的器件相比,电气性能也得到了改善,包括降低了约10-20%的接触电阻,相似的阈值和亚阈值特性,驱动电流和跨导提高约10%,以及更好的器件性能曲线。

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