This paper describes experimental results used to optimize the source/drain implant design of a dynamic threshold DTMOS n-channel device, fabricated within a low-cost 0.15μm SOI CMOS System-On-Chip process, which also included high-density embedded DRAM. A shallower, lower dose S/D implant was found to lower the body resistance and DIBL, thus increasing the dynamic body effect. The DTMOS device design in this process was previously found to be superior to both grounded body (GB) and floating body (FB) operation[1], with Ion=656μA/μm, Ioff=3pA/μm, S=64mV/dec, and Gm=1690μS/μm at Vdd=1.0V. This DTMOS device was also previously shown to have excellent analog and RF performance, with Fmax=32GHz. These characteristics permit embedded ultra-low-voltage analog circuits and RF front-end circuits in combination with embedded DRAM cores for ultra-low-power, low-cost SOCs.%描述了用以进行n-沟道动态电位DTMOS半导体器件源极/漏极载流子注入优化设计的实验结果,该器件制造采用了低成本0.15微米SOI和SOC(system-on-chip,系统集成芯片)技术,同时也包含了高密度嵌入式DRAM技术.实验结果表明,本器件可用来作为嵌入式超低压模拟电路和射频前端电路的混合电路芯片,并与嵌入式DRAM核心技术一起,作为超低压、低成本SOC(系统集成芯片)使用.
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