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The Experimental Measurement of Wire Sag of Long Wire Bonds for 3-dimensional and Multi-chip Module Packaging

机译:三维和多芯片模块包装长线键合线凹槽的实验测量

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Concerns about wire sweep and wire sag on the applications of the 3-dimensional packaging technology in the multi-chip module systems have been highly raised recently. Because the interconnection distance of the multi-chip modules is usually longer than that in single-chip system. It had been proved by authors' previous studies that the longer the bond length and the higher the bond height of a wire bond, the smaller the sweep stiffness of the bond system. The lower sweep stiffness of the wire bond will always cause higher risk of wire sweep which may induce device shorting and/or current leakage leading to IC failure. Therefore, most of the studies in the literature focus on how to precisely predict the wire sweep for a specific profile of wire bond. For 3-dimensional and multi-chip packaging, excessive wire sag can lead to wire touch to the lower layer and then cause short circuit and failure of chips. This paper will mainly study the wire sag problem for long wire bonds applied in 3-dimensional and/or multi-chip module packaging. A definition of the sag stiffness of a wire bond will be proposed to represent the sag resistance of a specific profile of wire bond. Furthermore, the wire sag experiments of wire bonds will be conducted to verify with numerical analysis.
机译:对多芯片模块系统中的三维包装技术应用的电线扫描和电线凹陷的担忧已经高度升高。因为多芯片模块的互连距离通常长于单芯片系统中的互联距离。作者以前的研究证明,键合长度越长,粘结的粘结高度越高,粘结系统的吹扫刚度越小。线键的较低扫描刚度将始终造成较高的线扫风险,这可能导致装置短路和/或电流导致IC故障的泄漏。因此,大多数文献集中在如何精确预测线摇摆的引线键合的特定配置的研究。对于三维和多芯片封装,过量的电线凹槽可以导致线路触摸到下层,然后导致芯片的短路和故障。本文将主要学习线松弛问题在3维和/或多芯片模块封装施加长引线键合。将提出线键的SAG刚度的定义来表示线键的特定型材的下垂抗性。此外,将进行线束的电线SAG实验以验证数值分析。

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