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The wire sag problem in wire bonding technology for semiconductor packaging

机译:半导体封装引线键合技术中的线垂问题

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摘要

Driven by the smaller, faster and cheaper demands of advanced microelectronic devices, the modern packages are required to increase I/O numbers, reduce die and package sizes and lower manufacturing costs. Although, today's microelectronic devices have many modern types of package, e.g. flip chip, wafer level packaging and tape automated bonding technologies, wire bonding is still the dominant microelectronic packaging technology. To provide more functions within a package, the 3-dimensional and multi-chip modules have come to be the solution of choice in delivering higher integration, smaller and more functional products for meeting consumer requirements, especially in the portable and handheld electrical products. Since the interconnection distance of the multi-chip modules is usually longer than that of a single-chip system, concerns about wire sweep and wire sag for the applications of 3-dimensional packaging technology in the multi-chip module systems have been highly mentioned recently. This has been ascertained by the author in previous studies, the longer the bond length and the higher the bond height of a wire bond, the smaller the sweep stiffness of the bond system becomes. The lower sweep stiffness of the wire bond will always cause higher risk of wire sweep. Consequently, for 3-dimensional and multi-chip packaging, excessive wire sag can lead to wire touch in the lower layer and thereby causing short circuits and malfunction of chips. Wire sag problems are very crucial to the applications of 3-dimensional and multi-chip packaging in semiconductor industry. To authors' knowledge, this issue has never been investigated. The main purpose of this paper will be to study in depth the wire sag problem for long wire bonds, applied in 3-dimensional and/or in multi-chip module packaging. A definition of the sag stiffness of a wire bond will be shown to represent sag resistance of specific profiles of wire bond. The author will also present wire sag experiments of wire bonds thereby verifying numerical analysis.
机译:在先进的微电子设备越来越小,更快,更便宜的需求的驱动下,现代封装需要增加I / O数量,减小管芯和封装尺寸并降低制造成本。虽然,今天的微电子设备具有许多现代类型的封装,例如倒装芯片,晶圆级封装和胶带自动键合技术中,引线键合仍是微电子封装技术的主导。为了在封装内提供更多功能,三维和多芯片模块已成为提供更高集成度,更小巧和功能更多的产品以满足消费者需求的首选解决方案,尤其是在便携式和手持式电子产品中。由于多芯片模块的互连距离通常比单芯片系统的互连距离长,因此近来已引起广泛关注关于在多芯片模块系统中应用三维封装技术的线扫和线垂的担忧。 。这已由作者在先前的研究中确定,键合长度越长,线键合的键合高度越高,键合系统的扫掠刚度就越小。引线键合的较低扫掠刚度将始终导致较高的引线扫掠风险。因此,对于3维和多芯片封装,过度的线垂可能导致下层的线接触,从而导致短路和芯片故障。线垂问题对于3D和多芯片封装在半导体行业中的应用至关重要。据作者所知,从未对此问题进行过调查。本文的主要目的将是深入研究用于3维和/或多芯片模块封装的长引线键合的引线下垂问题。将显示引线键合的抗流挂刚度的定义,以表示引线键合的特定轮廓的抗流挂性。作者还将介绍引线键合的引线下垂实验,从而验证数值分析。

著录项

  • 来源
    《Microelectronics & Reliability 》 |2013年第2期| 288-296| 共9页
  • 作者单位

    Institute of Mechatronic Engineering, Cheng Shiu University, Taiwan;

    Institute of Mechatronic Engineering, Cheng Shiu University, Taiwan;

    Institute of Mechatronic Engineering, Cheng Shiu University, Taiwan;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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