Ultra CSP~TM A Wafer Level Package

摘要

There has been a significant amount of work over the past 5 years on chip scale packaging. The majority of this work has been an extension of conventional IC IC packaging technology utilizing either wire bonders and/or tab type packaging technology. Handling discrete devices during the IC packaging for these type of CSPs hasresulted in a relatively high cost for these packages and lower IC package yields than desired. This paper will present a new wafer scale packaging technology called the Ultra CSP. Advantages of this wafer scale packaging concept includes commonality with standard IC processing technology for the majority of the packaging process.