WAFER-LEVEL CHIP SCALE PACKAGE (CSP) STRUCTURE AND PREPARATION METHOD THEREFOR

摘要

The present invention relates to a wafer-level chip scale package (CSP) structure and a preparation method therefor. The wafer-level CSP structure comprises a chip. A light-exiting surface of the chip is provided with a first-concentration fluorescent layer to form a package A, and less than 10% of the area of the light-exiting surface of the chip is covered by the first-concentration fluorescent layer. The top surface and side surfaces of the package A are further provided with a translucent or transparent second-concentration fluorescent layer to form a package B. The concentration of fluorescent powder in the first-concentration fluorescent layer is recorded as w₁, the concentration of fluorescent powder in the second-concentration fluorescent layer is recorded as w₂, and w₁w₂. The first-concentration fluorescent layer and the second-concentration fluorescent layer are formed by spraying fluorescent powder twice successively, thereby facilitating achieving a target value in process production, reducing the process difficulty, and improving the yield of devices. The wafer-level CSP structure of the present invention can improve the heat dissipation performance of light emitting chips, reduce the preparation costs of devices, and improve the reliability and uniformity of the devices.