A 1.9 ns BiCMOS CAM macro with double match line architecture

摘要

A 64-entry×32-b high-speed BiCMOS CAM (content addressablenmemory) macro is implemented on a 0.5 μm BiPNMOS sea-of-gates. Innorder to realize high-speed operation, a double match line (DML)narchitecture and a BiCMOS pull-up circuit are employed. The BiCMOSnpull-up circuit imparts high drivability to a second match-line driver.nA fabricated chip shows 1.9 ns of address-to-match delay time. The CAMnmacro also has high-density characteristics because a single CAM cellnoccupies only one basic cell of the gate array. Since the CAM macro isnimplemented on a gate array, the configuration can be altered easily andnquickly depending on customers' requests